1. Field of the Invention
The present invention relates to a semiconductor memory apparatus and more particularly, to a multiple-valued (MV) dynamic random-access-memory (DRAM) device capable of storing multiple value levels using a single electron transistor (SET) device.
2. Description of the Related Art
Recently, a research has been conducted on an SET. The SET has advantages of increasing the integration degree of a circuit and decreasing power consumption. The SET also has inherent characteristics that the drain current of the SET increases and decreases periodically according to a gate bias. Researchers have made an effort to increase functionality of a circuit with fewer transistors by using such characteristics. In particular, the SET device has been proven to have characteristics highly suitable for applications in a multiple-valued logic circuit and therefore, incessant efforts have been made to use the SET device for the multiple-valued logic circuit application.
FIG. 1 is a diagram for explaining a universal lateral gate 100 in which a single electron transistor (SET) device and a metal-oxide-semiconductor (MOS) transistor are coupled to each other.
Referring to FIG. 1, when a constant voltage Vgg is applied to the gate of a transistor M1, the drain voltage Vds of the SET is maintained at a constant voltage equal to Vgg-Vth. Since the voltage Vgg-Vth is low enough to satisfy a Coulomb blockage condition, the SET shows characteristics that the drain current of the SET increases and decreases periodically according to an input voltage Vin. In this case, a constant current Io is supplied from a constant current source to the drain of the SET.
When the input voltage Vin is changed so as to increase the drain current of the SET to a current higher than the current Io supplied from the constant current source, the output voltage Vout will be rapidly decreased from a high level to a low level. On the other hand, when the input voltage Vin is changed so as to decrease the drain current of the SET to a current lower than the current Io supplied from the constant current source, the output voltage Vout will be rapidly increased from a low level to a high level.
Therefore, when the input voltage Vin is increased, the output voltage Vout of the universal lateral gate 100 may have a square waveform with a high voltage swing.
FIG. 2 is a diagram showing an exemplary circuit of a quantizer 200 using the universal lateral gate 100 of FIG. 1.
Referring to FIG. 2, the constant current source provides a number of stability points and the quantizer 200 operates in stable regions defined by dotted lines between two neighboring stability points. More particularly, when a clock signal CLK is enabled, an input voltage Vin is transferred to a storage node SN through a transistor M2 and quantized to a stability point corresponding to the voltage after the clock signal CLK is cut off. Accordingly, it is possible to obtain an input-output (Vin-Vout) voltage characteristic similar to a stepped waveform.
The quantizer 200 having the SET device and the MOS transistor coupled to each other can be used for a memory application. In particular, since the quantizer 200 can store multiple level voltages without performing an additional refresh operation, it is highly effective in a multiple-valued static memory.
FIG. 3 is a circuit diagram showing a DRAM type multiple-valued (MV) static random-access-memory (SRAM) using the quantizer 200 of FIG. 2.
Referring to FIG. 3, an MV SRAM cell 300 includes a first transistor M1 connected between an SET and a storage node SN and having a gate connected to the ground voltage; a second transistor M2 connected between a power supply voltage Vdd and the storage node SN and having a gate connected to the storage node SN; a third transistor M3 connected between a bitline BL and the storage node SN and having a gate connected to a word line WL; and a cell capacitor Cs connected between the storage node SN and the ground voltage. The first and second transistors M1 and M2 are depletion transistors and the third transistor M3 is an NMOS transistor.
FIG. 4 is a timing diagram showing write and read operations of the MV SRAM shown in FIG. 3.
Referring to FIG. 4, during a write operation, the word line WL is enabled at t0. After the word line WL is enabled, a voltage corresponding to a multiple logic value is applied to the bitline BL at t1. In order to store two bits in each cell, voltages having four different levels need to be applied to the storage node SN through the bitline BL. When corresponding voltage levels are transferred to the storage node SN, the word line WL is cut off at t2 and the bitline BL is precharged to the ground voltage at t3. Accordingly, the voltage levels stored in the storage node SN are maintained without being refreshed in accordance with the principle of the stability point of an operation of the quantizer 200 in FIG. 2.
During a read operation, the word line WL is enabled at t4 and electric charges stored in the cell capacitor Cs are shared with a parasitic capacitor of the bitline BL. At t5, a sense amplifier is enabled so as to sense the multiple value levels.
However, since the MV SRAM cell includes four transistors and one capacitor, the chip size of the MV SRAM cell is increased. A multiple-valued memory is advantageous in that it increases storage density by increasing the number of bits stored in a cell but disadvantageous in that it decreases the number of device used in the cell, thereby defeating the advantages of the MV SRAM.
FIG. 5 is a diagram showing a 1T1C (1 transistor and 1 capacitor) cell of a DRAM.
Referring to FIG. 5, when electric charges are stored in a storage node Vs of a cell capacitor Cs, data is stored in the storage node Vs. The DRAM has a structure in which parasitic capacitors exist in bitlines and word lines. When the data is read from the DRAM, the electric charges stored in the cell capacitor Cs are shared with the parasitic capacitor of the bitline and the voltage level of the bitline is sensed, thereby reading the data.
FIG. 6 is a diagram for explaining a leakage current path viewed from the storage node Vs shown in FIG. 5.
Referring to FIG. 6, the electric charges stored in the cell capacitor Cs are decreased due to a junction leakage current and a sub-threshold current. Therefore, the level of the electric charges stored in the cell capacitor Cs is decreased over time. Accordingly, a refresh operation needs to be performed before the data is destroyed due to loss of the electric charge.
FIGS. 7 and 8 are diagrams showing a structure of a DRAM cell array and timings for a refresh operation.
Referring to FIGS. 7 and 8, the word lines WL are sequentially enabled for every refresh period tref before the electric charges stored in the cell capacitor Cs of the DRAM are lost. Thereafter, the voltage levels stored in the bitlines BL are sensed and amplified using a sense amplifier S/A and data is rewritten, thereby completing the data refresh operation. However, in the DRAM, a large amount of electric current is consumed in order to charge and discharge a relatively large parasitic capacitor of the bitline. Since this consumed electric current increases a standby current, the DRAM is not suitable for a low-power application.